1. Field of the Invention
The present invention relates generally to vertical synchronization processing circuits and, more particularly, to a vertical synchronization processing circuit for use in monitor receivers or the like.
2. Description of the Prior Art
Vertical synchronization processing circuits for use in a monitor receiver or the like are proposed to count a horizontal synchronizing signal and generate a vertical synchronization timing signal or the like from the count value (known as "count down processing").
FIG. 1 of the accompanying drawings shows in block form an arrangement of a conventional vertical synchronization processing apparatus.
Referring to FIG. 1, a vertical synchronizing signal applied to an input terminal 61 is supplied through an input inhibit gate 62 to a reset terminal of a counter 63. A clock signal synchronized with a horizontal synchronizing signal is supplied from a terminal 64 to the counter 63 and is thereby counted. When a count value reaches a predetermined value, a vertical deflection timing signal, for example, is developed at an output terminal 65 from the counter 63. Further, this count value is supplied to a window setting logic circuit 66 which then forms a detection window of the vertical synchronizing signal. The detection window is supplied to the input inhibit gate 62. When the vertical synchronizing signal is not detected during the detection window period, then a reset signal corresponding to the end of the detection window period is supplied from the logic circuit 66 to the reset terminal of the counter 63.
In the above-mentioned conventional apparatus, however, the detection window is formed of a hard logic so that only detection windows of about one to three kinds in a fixed range can be provided. On the other hand, the detection window cannot be reduced too much in width because a non-standard signal such as signals used in a variable speed playback mode of a video tape recorder must be taken into consideration. There is then the large possibility that a noise or the like, which might be mis-detected, occurs in the vertical synchronizing signal within the detection window. Therefore, there is then the large risk such that a malfunction or the like occurs due to the mis-detection.
Further, in the above-mentioned conventional apparatus, when the vertical synchronizing signal is not detected within the detection window, the counter 63 is reset at the end of the detection window period and the vertical synchronizing signal is interpolated by this resetting of the counter 63. As a result, a jitter component occurred due to this interpolation. Further, since distributions of vertical synchronizing signals are different depending upon input signals, the distribution is not always located at the center of the detection window. Therefore, it is frequently observed that the amount of jitter components is changed when the distribution of the vertical synchronizing signal is located in the first or second half of the detection window.